AMD's EPYC Venice lands: Zen 6 on TSMC 2nm, 256 cores, and a record server share
A unified 2nm CCD design, up to 256 cores, 16-channel DDR5, PCIe 6.0, and the first HPC product in production on TSMC's 2nm process.
AMD this summer unveiled its sixth-generation EPYC “Venice” server processors at its Advancing AI event in San Francisco, and the lineup marks the most substantial data-center CPU step forward the company has made in years. Venice was formally launched on July 22–23, 2026, following a May 21 production-ramp confirmation that the chips were already coming down the line at TSMC's fabs in Taiwan, with future ramp capacity planned at TSMC's Arizona facility. AMD frames it as the first high-performance computing product in the industry to enter production on TSMC's advanced 2nm process technology.
The architecture shift is more than a node shrink. Zen 6 moves both the high-performance cores and the dense Zen 6c cores onto the same 2nm process, breaking a pattern from the Turin generation where the two CCD types used different nodes. Every CCD pairs 4MB of L3 cache per core, roughly double the L3 per core of Zen 5's dense design: up to 384MB on high-performance parts and up to 1,024MB on the flagship EPYC 9996, which also carries a 600W TDP, a 4.1GHz boost, 128 PCIe 6.0 lanes, and a 16-channel DDR5 memory controller delivering over 1.6TB/s of aggregate bandwidth.
Core counts stretch to the dense end of the family. The EPYC 9006 dense series (Venice-X) tops out at 256 cores and 512 threads, 33% more than the 192-core Turin dense parts, while high-performance Venice tops out at 96 cores on new SP7 and SP8 sockets, stepping up from EPYC's long-running SP5 platform. Memory bandwidth and PCIe 6.0 both jump generations, and AMD says the platform's aggregate performance target is roughly 70% ahead of the previous generation.
Markets are already moving before shipping silicon. Industry reporting pegs EPYC Venice at a record 46.2% server market share heading into launch, with systems targeted to begin shipping to customers in Q3 2026 and Helios platform and MI450-series paired configurations dependent on HBM4 allocation. Venice also lands alongside AMD's Instinct MI400-series GPUs, all of which are built on the same 2nm tapeout, tightening the CPU-accelerator pairing AMD has been chasing against the hyperscalers.
What's in the Venice family
- EPYC 9006 (Venice): Zen 6, up to 96 cores / 192 threads, up to 384MB L3, SP7/SP8 sockets
- EPYC 9006 dense (Venice-X): Zen 6c, up to 256 cores / 512 threads, up to 1,024MB L3
- Flagship EPYC 9996: 600W TDP, 4.1GHz boost, 128 PCIe 6.0 lanes, 16-channel DDR5, 1,024MB L3
- 16-channel DDR5 with over 1.6TB/s aggregate memory bandwidth, doubled from the 12-channel Turin design
- PCIe 6.0 host interface, a full generation ahead of EPYC Turin's PCIe 5.0
- Both CCD variants built on TSMC 2nm on the same process node, unlike Turin's mixed-node design
Venice is the first HPC part in production on TSMC 2nm, and its unified two-variant, single-node design gives AMD a cleaner performance-per-watt story than Turin. A 46.2% server share heading into launch is a record for EPYC, and pairing 256-core dense chips with 2nm MI400-series accelerators gives AMD a coherent “whole node” platform argument against hyperscaler rivals.
If you're planning datacenter refreshes or cloud budgets into 2027, Venice-era platforms are where the 2nm-era CPU supply starts. Expect SP7/SP8 boards, 16-channel DDR5 memory kits, and PCIe 6.0 add-in cards to become the new baseline for high-core-count server workloads, with dense 256-core SKUs targeted at AI training, large-scale virtualization, and scientific HPC workloads that previously belonged only to the highest-end Turin parts.
Sources: AMD Newsroom: Production ramp of AMD EPYC “Venice” on TSMC 2nm; ServeTheHome: Inside EPYC Venice, 256 Cores, 2nm; Tom's Hardware: AMD's enterprise CPU and GPU roadmap (Venice, Verano, Zen 6, Helios).
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