How RISC-V Instruction Sets Work

What a processor is really built from

A processor does not come into existence as a finished chip. Long before any silicon is ordered, an engineer defines the instruction set architecture, or ISA: the complete catalog of machine-level operations the processor can perform, how data moves between registers, and how software talks to the machine. The ISA is the contract between the hardware that executes instructions and the compilers and operating systems that generate them. If the contract is stable, software written once runs on any implementation that honors it, which is the entire reason the concept exists.

RISC-V is the newest major attempt to make that contract free and public. It is a reduced instruction set computer architecture defined as a set of open standards maintained by RISC-V International, a nonprofit founded in 2015 when the RISC-V work was spun out of the University of California, Berkeley. Unlike the proprietary ISAs of Intel and ARM, the RISC-V specifications are published openly. Anyone can read the full definition of every instruction, implement a core, and sell it without paying the architecture owner a royalty on the base set. That openness is the single fact that makes everything else about RISC-V possible.

The base integer set and XLEN

The core of RISC-V is the integer instruction set, known as RV. It starts from a small number of load and store data types and a fixed set of operations: arithmetic and logic across the register file, memory loads and stores, and branch and jump control flow. The whole design deliberately favors small, well-defined instructions that retire in a pipeline over large, variable ones, which keeps hardware simpler and more predictable.

The base set comes in two sizes, distinguished by the width of the general-purpose register file and the native data path: RV32, where registers and native words are 32 bits, and RV64, where they are 64 bits. A third, RV128, exists for very wide designs. This register width is called XLEN, and it is the knob that lets the same architecture scale from a tiny embedded microcontroller to a full workstation-class processor. Software that targets RV32 compiles into 32-bit addressing; software that targets RV64 gets 64-bit pointers and wider integer math. An RV32 core and an RV64 core are different, but they share the same underlying philosophy and the same extension framework.

The base integer set is deliberately incomplete on its own. It handles computation and control flow but says nothing about floating point, compressed instructions, or atomic operations. RISC-V answers this with optional extensions, each labeled with a single letter. The C extension provides compressed 16-bit encodings that shrink code size roughly 30 percent with a negligible instruction set. The M extension adds integer multiplication and division. The A extension adds atomic memory operations so software can build lock-free structures and synchronization primitives. The F and D extensions add single and double precision floating point. The string that names a processor is just these pieces combined, which is why you see names like RV64GC, meaning a 64-bit core with the general and compressed extensions enabled.

Profiles, privmodes, and where the ecosystem goes

Because extensions are optional, a vendor could in principle enable a strange and useful-incompatible combination. To keep software portable, RISC-V International defines profiles, named packages that bind a required base ISA together with a set of mandatory and optional extensions. A profile like RV64GC is the workhorse for general computing, while smaller embedded profiles target microcontrollers that cannot afford the register file or the instruction width of a server core. Profiles are what turn loose flexibility into a portable contract: a compiler or library that targets a named profile knows exactly which instructions it may assume.

The architecture layers privilege on top of the register file. The U extension defines a user mode for running untrusted applications, the S extension defines a supervisor mode where the operating system lives, and the M machine mode is the most privileged level, where firmware and reset code run. This three-level hierarchy mirrors the trust model of established ISAs and is what lets a RISC-V core run a full operating system such as Linux alongside protected user applications. Because the specification is open, the same layers are available to hobbyists and to datacenter builders alike, which is why open cores built on RISC-V now anchor a surprising amount of the world's silicon.

The spread of RISC-V is no longer limited to embedded work. It now appears in NVIDIA and other AI compute accelerators, in RISC-V server-class cores from multiple vendors, in trusted execution environments, and in security-adjacent roles where an open, auditable instruction set matters more than the last few percent of performance. Vendors can also add their own custom extensions without changing the base, and the standardization process allows new instructions to graduate from custom into ratified, portable status over time. The result is a processor world where the foundation is a public set of documents, not a single company's roadmap.

If you are a developer, the practical takeaway is that RISC-V is a portable, royalty-free target and a growing one. Toolchains from LLVM and GNU support it, and the base set is small enough to learn, so it has become a popular teaching architecture and a low-risk target for embedded and security-sensitive work. If you are an engineer choosing hardware, the base ISA plus profiles tells you exactly what a core can do and where its vendor-specific additions begin. And if you are watching where computing is heading, the fact that an open standard now spans everything from microcontrollers to the accelerators driving current AI workloads is the quiet, durable story underneath all the specific products.

Sources: RISC-V International Foundation Overview; RISC-V Base Integer Instruction Set Manual (ratified).

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